Deliver and implement advanced verification solution by utilizing Synopsys Verification product portfolio. The engineers need to act as a strong team member and contributor. Exercise judgment within generally defined practices and policies. Specific responsibilities include: Deep understanding on ASIC design and verification flow. Excellent knowledge of advanced verification methodology. Good in System Verilog, System C and using Verification components (VIP). Experienced on developing and using assertion based verification and formal analysis method. Skilled in scripting language like Perl, C shell, Python, Makefile.
Position Requirement:
Must have BS degree with 5+ years of applicable experience, MS degree with 3+ years of applicable experience in microelectronics, electrical engineering. Essential that the candidate demonstrates strong communication skill. Have demonstrated successful completion of 6+ design projects as an individual contributor. Demonstrated hands on experience and expertise with EDA verification tools, flow and methodologies required to execute verification projects. Need to demonstrate successful completion of 3+ verification projects as individual contributor. Memory IP project verification experience is preferred.
