Responsible for the design and development of analog mixed signal Serdes/AFE/High-speed IO macros from initial concept/specification to final verification and match the design requirements. Candidates should have experience on high speed Serdes designs and have good knowledge on common Serdes standards or AFE or high speed IO including electrical requirements. Candidates must have deep design experience in one of the following Serdes blocks: Driver; ADC/DAC; Receiver; Serializer; Deserializer; Phase Interpolator; Low Jitter PLL; High Speed Clock Distribution.
Position Requirement:
Must have BS degree with 7+ years of applicable experience, MS degree with 5+ years of applicable experience in microelectronics, electrical engineering. Candidate must be able to own a block or set of blocks for analog SerDes/AFE/high speed IO IC design. Candidate needs to be familiar with the design process, required handoffs to the top-level design team for smooth integration, and robust block verification. Proficiency in using EDA tools for circuit simulation, layout and physical verification with the design experience at more than 6.25Gbps and in <40nm technologies are preferred.
